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| Comp-Arch | EDA & Tools | VHDL | Verilog | Newsletter | | Asynchronous | Synthesis | Books & Reviews | |
An ultimate example of the power of HDLs.
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VLSI Training: Design: VHDL, Verilog Verification: Specman, System Verilog (SV), SVA, PSL, ABV... Contact(Web): http://www.vlsitraining.net Contact(Email): info@vlsitraining.net |
Computer Architecture
Computer Architecture pages spread across various sites, including CPU Architecture. |
Knowledge
capsule HDLPlanet's knowledge sharing initiative. The latest edition is here Nov 2003. |
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VHDL
Introduction to VHDL, how to get started with it, tool kit requirement for getting started, links to VHDL learning resources, tutorials and books and also contains pointers to libraries containing free VHDL models. |
Verilog
Verilog, learning resources and some good pointers to other verilog pages on the web. Getting started with Verilog, tutorials and models. |
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Synthesis Fundamentals of synthesis. Some examples of synthesizable structures. |
Asynchronous
Design Fundamentals of asynchronous design and its advantages. |
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EDA & Tools
Pointers on introduction to EDA, information on scripting requirements in Design Automation, and details of some EDA Tools available and their brief description. |
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Last Updated on 14th Jan 2005 |
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