Make your own free website on Tripod.com

Implementation of Memory Test Controller and design of Control Logic for Repair Module

Deepa.V.H, (1DA04LVS03), MTech, Dr. Ambedkar Institute of Technology


ABSTRACT

Testing semiconductor memories is increasingly important today because of the high density of current memory chips. This paper presents an overview of testing and repairing of semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly and the control logic of the repair module that can be used. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are discussed throughout the paper. Test procedures for these fault models are presented which are widely used today for testing chip level, array level and board level functional memory defects. Repairing of the memory includes replacing the rows and columns which have maximum errors with the redundant rows and columns present in the memory.

To read the full paper "Click Here"


get this gear!


Date : 31st May 2006