|The Very first question that can arise would
be "What does VHDL
stand for ?"
VHDL stands for VHSIC Hardware Description
and VHSIC in turn stands for Very High Speed
VHDL is an industry standard language used to describe hardware from the
abstract to the concrete level. VHDL is rapidly growing in popularity &
it is being embraced as the universal communication medium of design. The
EDA vendors support VHDL both in & out of their tools (Simulation tools,
Synthesis tools, & Verification tools).
- VHDL, A Simulation Modeling Language
VHDL has ample features appropriate for describing the behavior of electronic components ranging from simple logic gates to complete
Microprocessors, high performance Digital Signal Processors and custom chips. Features of VHDL allow
timing aspects of circuit behavior (such as rise and fall times of signals,
delays through gates, and functional operation) to be precisely described. The resulting VHDL
simulation models can then be used as building blocks in larger circuits (using schematics, block
diagrams or system-level VHDL descriptions) for the purpose of simulation
- A Design Entry Language
Analogous to any high-level programming languages like Pascal & C,
which allow complex design concepts to be expressed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a
design system for automatic circuit synthesis or for system simulation. VHDL includes features useful for structured design techniques, and offers a rich set of control and data
representation (most useful for modeling current day high performance
microprocessors and digital signal processors) features. One other feature is
that, hardware being described in VHDL is inherently concurrent analogous to
the actual hardware behavior. However those who have experience with just the
programming languages, have some new concepts to grasp.
- A Verification Language
VHDL being a powerful language is capable of enabling the development of
the verification environment. This is most commonly referred to as a
"Test Bench" which contains the descriptions of circuit stimulus and
corresponding expected outputs that verify the behavior of the circuit known
as "Device Under Test (DUT)" over the time. This feature is most of
the time under-utilized. Test benches should be an integral part of any VHDL
project and should be created in parallel with the development of the
functional modules. Have a look at VHDL Verification
section to learn more about VHDL's Verification capabilities
- A Netlist Language
VHDL with its ability to support structural representation of circuits, is
very useful as a low-level form of communication between different tools in a
computer-aided design environment. These features of VHDL allow it to be
effectively used as a netlist language, replacing (or augmenting) other
netlist languages such as EDIF (Electronic Design Interchange Format).
- As Simple or Complex u want it to be
One of the most compelling reasons for you to become experienced with and knowledgable in VHDL is
its adoptance as a standard in the electronic design community. While it is
believed that VHDL is a large and complex language, it is not actually
difficult to get started with. Use it as you need, explore the advanced
features as you become more confident, and clarify your doubts on the news
groups (http://groups.yahoo.com/group/hdlplanet). It won't take long before
you get confident and master this wonderful language.
|The next possible question would be "What
is the History of VHDL ?"
Well, this is not the place to discuss about the past of VHDL. Here
our focus is to, how best we can utilise the capabilities of VHDL to develop
a desired system. However it is worth looking at the 10,000 feet overview
of VHDL's past. VHDL is the child of VHSIC program funded by the Dept.
of Defense in US during 1970s to 1980s. It was established as the
IEEE 1076 standard in 1987. In 1993, the IEEE 1076 standard was updated
& an additional standard, IEEE 1164 was adopted. In 1996, IEEE 1076.3
became the VHDL synthesis standard.
|Its quite possible that u may be having 100 other questions,
and obviously you are not the first one to ask these questions, many others
have asked the same questions before and yes... they have been collected
and made available to everyone in a FAQ repository. No follow the below
links and find the answers yourself:
The VHDL FAQ - This
FAQ is divided into 4 sections and is posted monthly to the VHDL Newsgroup
FAQ General (contacts, etc.)
Lists of Books on VHDL
Lists of Products & Services (Freewares and Commercial stuff)
Yes, its quite possible that your question might not have been answered
yet, then u can definitely go and post your question in the newsgroup comp.lang.vhdl
and be assured, u will find the answer. Haven't heard of this newsgroup
yet ? Well in that case u should know what is told about the newsgroup:
"The newsgroup comp.lang.vhdl was created in January
1991. It's an international forum to discuss ALL topics related tothe language
VHDL which is currently defined by the IEEE Standard 1076/93. Included
are language problems, tools that only support subsets etc. but NOT other
languages such as Verilog HDL. This is not strict - if there is the need
to discuss information exchange from EDIF to VHDL for example, this is
a topic of the group. The group is unmoderated. Please think carefully
before posting - it costs a lot of money! (Take a look into your LRM for
example or try to search http://www.Deja.com/usenet - if you still cannot
find the answer, post your question, but make sure, that other readers
will get the point). "
|Next possible question is, "How
do I get started with VHDL ?"
Very simple, u just read thru' this page and u will get
all the stuff u need to know before u get started with VHDL. Primarily,
what one can think of is some tools with which u can learn VHDL. What are
those tools now ? Yes, u need an Editor to write your VHDL code.
Being a beginner u would of course look for some sort of free editors:
If you come across any other better editors, do let me know and that will
help others know it.
Emacs / Xemacs
is the best bet as I would suggest. You can also get VHDL mode for it for
syntax highlighting. It is the most preferred as I would say. This is normally
used under unix platforms (may it be Linux of Solaris). An emacs close
does exist for Windows users too, NTemacs,
though I haven't tried it.
Next option is the standard editor since ages, Vi
/ Vim. You can download the latest Vim release and use it. It has got
syntax highlighting for VHDL.
Next comes the Simulation Tools. Oh!! I really forgot to tell u " What
Simulation is a process in which the designed model of
an actual component is exercised for analyzing its behaviour under a given
set of conditions and/or stimuli. With this definition, a simulation run
requires a model of the component being simulated & a set of stimuli
for activating the model. A simulator is a tool which simulates
the model with our stimuli & produces the simulation result which is
an indicator for the behaviour of the model. We shall come to questions
like "How many types of simulations are there ? & what are the differences
between them" at a later stage.
Now coming back to Simulators for beginners, yes
there are quite a few of them like GMVHDL, PeakVHDL etc., but its very
difficult to say which one is the best. One has to try a couple of tools
and see which he feels better. Anyway, I'll give my opinions and its up
to u to dig out further:
Next comes the Synthesis Tools, yes now is the time
to tell you "What is Synthesis ?"
For a beginner I would suggest Alliance
Simulation Tool (asimut). I am not saying that it is the best ever
tool a beginner can find, but it is very simple to use and u need not break
your head on learning a lot at once. Of course there are some limitations,
this supports just a subset of VHDL and to understand the concept involed
this is no less than any other tool. Not to forget this works on unix-like
platforms (Linux and Solaris).
If you feel that u wish to start off with a better tool then
it is better to go for Vanilla
CAD Tools along with a Waveform
Viewer under Linux Platform.
For Windows worshipers, VHDL
Simili from symphonyEDA would be a better choice.
If one thinks that a little money spent can fetch a better
stuff, then try out Active-HDL
from Aldec. Inc. If I am not wrong they
do have a trial version, which u can try and purchse on being satisfied.
Well, finally its not a god thing to end the simulators section
without telling which is the BEST SIMULATOR in industry. It is "Modelsim"from
Model Tech. Beginners, don't ever think of looking at its price. Even the
industries think twice before opting for an additional modelsim license. A 30
day evaluation version
is always available. Ofcourse this a memory limited version. This can support a
maximum of 7MB.
One other good option for a beginner is going for Xilinx
WebPack, which includes a free modelsim simulator (ModelsimXE). This is one
best simulator anyone can think of. Look at the Feature
Support Matrix to know more about the WebPack capabilities.
Synthesis is a blanket term which refers to the
automatic translation of HDL code into an equivalent netlist of digital
cells. The tools which handle this conversion task are "Synthesis tools".
Essentially a synthesis tool is a collection of artificial intelligence
(AI) programmes which interpret, optimize & retarget designs expressed
in an HDL. The current synthesis tools available today convert Register
Transfer Level (RTL) descriptions to gate-level netlists. The gate-level
netlists consist of interconnected gate-level macro cells. The models for
gate-level cells are contained in technology libraries for each type of
technology supported. The gate-level netlists currently can be optimized
for area, speed, power, testability, etc. We shall go into the details
Now getting back to the Synthesis Tools:
I strongly suggest Alliance
Synthesis Tools (FPGEN, DPR, DPP, SCR, etc) here. This is one excellent
set of synthesis and backend tools that come for free. I have tried these
they are simply superb. This is one reason I suggested Alliance Simulator
too, because one bunch of tools can do everything for u, from Simulation
to Synthesis to Physical Design.
I have heard of one other tool, MyCAD
which I am yet to try and it would be a wrong thing to comment on this
without fiddling with it. But as I've heard this is also a good evolving
tool. In case u use this do let me know its performance.
Again the industry standard here is to tool from Synopsys
which has no equivalent as I would say. A piece of advice for beginners,
forget using this at home.
WebPack is again a good option for a beginner since it has got a
synthesis tool in the package. Have a look at its Feature
It is just not enough to have all the essential tools in place. It
is more essential to know and learn VHDL in full. Only then its possible
for u to reap the fruits those tools are capable of giving out. A few good
online VHDL tutorials and books are given below.
After Learning VHDL, it is good to have a look at some of the VHDL
models available on the web. It may be helpful in many ways. Following
are a list of places of web where one can find loads of VHDL models.
The RASSP Technology Base developing
VHDL models of selected standard integrated circuits. -> list
The Free Model Foundation
They provide free VITAL compliant VHDL models. Make sure to add your
own models with them! FMF-Library
Models and Packages (Hamburg VHDL Archive)
You get there: IEEE package, Numeric std arithmetic package for synthesis,
Mathematical package, several microprocessor models, memory and glue-logic
The TIREP Project
(Technology Independent Representation of Electronic Products) The project
was directed toward the generation of a paperless design specification,
based upon VHDL.
of the month (Archive)
to Francis Bruno: "VHDL: An introduction"
Strasbourg (VHDL-Database server of the MACAO/Phase team)
Many models and packages, but be patient, the server is slow! Click
here to search the list of models
University of Pittsburgh.
Models in directory EXAMPLES!
Free VHDL core models from OpenCores
Commercial Sites: look at Model
Verification is an important phase in an ASIC design cycle. I would say
this is more important than the design phase itself. It is the quality of our
product that gets certified in this phase and we can't trade-off this with any
other phase. At this point we are more concerned about the functionality of
model we have designed and its adherence to the design specifications. A
brief note on how VHDL enable verification.
Verification Course : A good page with a collection of
details regarding various verification strategies in VHDL. (A site by