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 Verilog
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Introduction to Verilog
Verilog is a hardware description language (HDL), similar to VHDL,  that was originally written by Phil Moorby in 1984. Phil Moorby was an employee of Gateway Design System Corporation. It was developed by Gateway Design Automation as a simulation language. Cadence purchased Gateway in 1989 and, after some study, placed the Verilog language in public domain. Open Verilog International (OVI) was created to further develop Verilog language as an IEEE standard. The definitive reference guide to Verilog language is the Verilog LRM, IEEE Std 1394-1995. You can obtain a copy of the IEEE standard through the IEEE
Verilog is a fairly simple language to learn if you are familiar with C programming language. However it is necessary to a little knowledge of hardware design to harness the full potentials of Verilog. 

 

Next possible question is, "How do I get started with Verilog ?"

Very simple, u just read thru' this page and u will get all the stuff u need to know before u get started with Verilog. Primarily, what one can think of is some tools with which u can learn Verilog. What are those tools now ? Yes, u need an Editor to write your Verilog code. Being a beginner u would of course look for some sort of free editors:

  • Emacs / Xemacs is the best bet as I would suggest. You can also get Verilog mode for it for syntax highlighting. It is the most preferred as I would say. This is normally used under unix platforms (may it be Linux of Solaris). An emacs close does exist for Windows users too, NTemacs, though I haven't tried it.
  • Next option is the standard editor since ages, Vi / Vim. You can download the latest Vim release and use it. It has got syntax highlighting for Verilog.
If you come across any other better editors, do let me know and that will help others know it.

Next comes the Simulation Tools. Oh!! I really forgot to tell u "What is Simulation?"
Simulation is a process in which the designed model of an actual component is exercised for analyzing its behaviour under a given set of conditions and/or stimuli. With this definition, a simulation run requires a model of the component being simulated & a set of stimuli for activating the model. A simulator is a tool which simulates the model with our stimuli & produces the simulation result which is an indicator for the behaviour of the model. We shall come to questions like "How many types of simulations are there ? & what are the differences between them" at a later stage.

  • "Modelsim"  from Model Tech. is the BEST SIMULATOR in the industry. Beginners, don't ever think of looking at its price. Even the industries think twice before opting for an additional modelsim license.
  • As a beginner 'am sure one would be looking for a free simulator. For those who like it free, its Veriwell which is pretty decent in its functionality. You can get its manual from Verilog Manual  This is also a good starting point for Learning Verilog. You can also get a PDF version of this manual at Verilog Manual (PDF) 
  • Once can use SILOS simulator also. It is available for Windows ME/2000/NT/98 platforms and the limitations of this Silos Demo software are 200 gates and 350 lines of behavioral code. U can look at other softwares available by Simucad at http://www.simucad.com
  • Some Verilog based tools are avaiblable at http://www.veripool.com/ 
 

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