| Comp-Arch | EDA & Tools | VHDL | Verilog | E-group Extracts |
Verilog is a hardware description language (HDL), similar to VHDL, that was originally written by Phil Moorby in 1984. Phil Moorby was an employee of Gateway Design System Corporation. It was developed by Gateway Design Automation as a simulation language. Cadence purchased Gateway in 1989 and, after some study, placed the Verilog language in public domain. Open Verilog International (OVI) was created to further develop Verilog language as an IEEE standard. The definitive reference guide to Verilog language is the Verilog LRM, IEEE Std 1394-1995. You can obtain a copy of the IEEE standard through the IEEE.
Verilog is a fairly simple language to learn if you are familiar with C programming language. However it is necessary to a little knowledge of hardware design to harness the full potentials of Verilog.
|Next possible question is, "How
do I get started with Verilog ?"
Very simple, u just read thru' this page and u will get all the stuff u need to know before u get started with Verilog. Primarily, what one can think of is some tools with which u can learn Verilog. What are those tools now ? Yes, u need an Editor to write your Verilog code. Being a beginner u would of course look for some sort of free editors:
Next comes the Simulation Tools. Oh!! I really forgot to tell u "What
Verilog Information on WWW
[note: "Verilog-2001" has also been referred to as "Verilog-2000", because the standard was completed in 2000,and it was originally expected that the IEEE would ratify the standard in 2000].