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 Synthesis (contd)
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Value Holders

Signals and Variables are the two classes of data objects available in VHDL that can be used to model the basic value holders in hardware. The basic value holders in hardware are wire, latch (a level sensitive device) & flip-flop(an edge triggered device).

In VHDL, a signal, or a variable declared in a process, retains its value during the entire simulation run thus inferring memory/storage element. But this becomes too general description of signal or variable. Infact whether a signal or a variable infers memory depends on the context of use and lets see that in a couple of examples.....

signal sig_1, sig_2, sig_3, sig_4;
.......
process (sig_1, sig_2, sig_3)
  variable var_5;
begin
  var_5 := sig_1 and sig_2;
  sig_4 <= sig_3 or var_5;
end process;

In the above example, variable var_5 is assigned first and used later in the right hand side expression of the second statement. Since the variable is being used immediately after its definition (assignment), there is no necessity for to store the value of var_5 though VHDL semantics indicates that it retains its value during its entire simulation run. Logic inferred in this case is an AND gate followed by an OR gate.

Now what if the variable is used before being assigned ??

begin
  sig_4 <= sig_3 or var_5;
  var_5 := sig_1 and sig_2;
end process;

In this case, variable var_5 is being used before it is assigned a value. This tries to use its previous value which would obviously mean a memory in place. However, it is not clear how to build a latch for variable var_5 because var_5 isn't assigned under the control of any condition. A synthesis system may issue an error or warning for using var_5 before assigning it. However, it again results in the same hardware an AND gate followed by an OR gate. But simulation results pre & post synthesis may not match!!!

 

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Now what would differ if var_5 was a signal ??  (lets call it sig_5)

signal sig_1, sig_2, sig_3, sig_4, sig_5;
.......
process (sig_1, sig_2, sig_3)
begin
  sig_5 := sig_1 and sig_2;
  sig_4 <= sig_3 or sig_5;
end process;

This is again the same case, sig_5 is being used before its assignment however there is no details specified about how a memory element could be built for sig_5. Again there could be mismatch in the simulation results between pre & post synthesis. Hardware inferred here is again the same AND gate followed by an OR gate.

If the simulation results for pre & post synthesis in the above example to match, the sensitivity list should contain sig_5 also.

Now lets add conditional assignment to it and see what happens:

begin
  if (enable = '1') then
    var_5 := sig_1 and sig_2;
  end if;
  sig_4 <= sig_3 or var_5;
 end process;

The only difference here is that we have provided additional information for the synthesis tool on how to build a latch for the variable var_5. Yesss.... the result is a latch for var_5.

How is a flip-flop inferred ?? This depends on the modeling style being followed and the context under which a variable or a signal is assigned. This is discussed in the sections above describing sequential logic synthesis or look at the next section to get a brief idea about register inferrance.

 

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Register / Latch Inferrance & Avoidance

Registers are always inferred when signals are assigned within clocked processes.

However rules differ for inferring a register for variables. 

  • Reading a variable before assigning some value to it defines a register implementation for that variable.

  • In case where a variable is assigned before being used, and if there are no conditions that could prevent its assignment, then there is no register implied for that variable. Suppose that variable is further used on the right hand side to assign some other signal, then register could be implied for the assigned signal only and not for the variable.

  • If a variable is used as a control element in either an IF construct or a CASE, then it is used in the generation of a control logic. Thus, if a register is not intended, it is important not to read the variables before assigning value to it.

A latch is generally inferred when all conditional signal assignments, and conditional statements are incomplete. So latches can be avoided by following avoidance rules:

  • All conditional signal assignments & conditional statements must be complete. All conditions must be considered and values must be assigned under all conditions.

  • Right hand side expression in a signal assignment must not depend on the values assigned during the previous activation of the process.

  • Sensitivity list must be complete.

  • Signals or variables that are assigned / defined within a clocked process must not be assigned again outside the process.

  • Within a single process where an IF construct separates the combinational logic & sequential logic, the variable / signal being assigned under clocked IF construct shouldn't be assigned again a different value outside the clocked IF construct. An example for this is a d flip-flop with an asynchronous reset. Here the IF construct separates combinational & sequential logic.
                  IF reset = '1' THEN
                      q <= '0';
                  ELSE IF clk'EVENT and clk = '1' THEN
                      q <= d;
                  END IF;

  • If a conditionally assigned variable is updated within a clocked IF construct, then that variable shouldn't be used / read outside that IF statement.
                  IF clk'EVENT and clk = '1' THEN
                        var_5 := not var_5;
                   END IF;
                   S2 <= var_5;

  • Avoid a conditional assignment which doesn't contain a 'event attribute within the condition unless a latch is explicitly meant.

 

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Latch Inferrance in Functions 

Variables declared within functions do not retain values assigned across calls to a function. Hence latches will not be inferred by synthesis. This holds good even if all latch inferring criteria are satisfied. However as a good coding practice, adopting non-latching coding style in functions is better than having confusions around it.

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Last Updated on 27th Jan 2002

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