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Value Holders
Signals and Variables are the two classes of data objects available in VHDL that can be used to model the basic value holders in hardware. The basic value holders in hardware are wire, latch (a level sensitive device) & flip-flop(an edge triggered device). In VHDL, a signal, or a variable declared in a process, retains its value during the entire simulation run thus inferring memory/storage element. But this becomes too general description of signal or variable. Infact whether a signal or a variable infers memory depends on the context of use and lets see that in a couple of examples.....
In the above example, variable var_5 is assigned first and used later in the right hand side expression of the second statement. Since the variable is being used immediately after its definition (assignment), there is no necessity for to store the value of var_5 though VHDL semantics indicates that it retains its value during its entire simulation run. Logic inferred in this case is an AND gate followed by an OR gate. Now what if the variable is used before being assigned ??
In this case, variable var_5 is being used before it is assigned a value. This tries to use its previous value which would obviously mean a memory in place. However, it is not clear how to build a latch for variable var_5 because var_5 isn't assigned under the control of any condition. A synthesis system may issue an error or warning for using var_5 before assigning it. However, it again results in the same hardware an AND gate followed by an OR gate. But simulation results pre & post synthesis may not match!!!
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Now what would differ if var_5 was a signal ?? (lets call it sig_5)
This is again the same case, sig_5 is being used before its assignment however there is no details specified about how a memory element could be built for sig_5. Again there could be mismatch in the simulation results between pre & post synthesis. Hardware inferred here is again the same AND gate followed by an OR gate. If the simulation results for pre & post synthesis in the above example to match, the sensitivity list should contain sig_5 also. Now lets add conditional assignment to it and see what happens:
The only difference here is that we have provided additional information for the synthesis tool on how to build a latch for the variable var_5. Yesss.... the result is a latch for var_5. How is a flip-flop inferred ?? This depends on the modeling style being followed and the context under which a variable or a signal is assigned. This is discussed in the sections above describing sequential logic synthesis or look at the next section to get a brief idea about register inferrance.
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Register / Latch Inferrance & Avoidance
Registers are always inferred when signals are assigned within clocked processes. However rules differ for inferring a register for variables.
A latch is generally inferred when all conditional signal assignments, and conditional statements are incomplete. So latches can be avoided by following avoidance rules:
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Variables declared within functions do not retain values assigned across calls to a function. Hence latches will not be inferred by synthesis. This holds good even if all latch inferring criteria are satisfied. However as a good coding practice, adopting non-latching coding style in functions is better than having confusions around it. |
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Last Updated on 27th Jan 2002 |
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