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library ieee;
use ieee.std_logic_1164.all;

entity dff_sync_res is
    port ( in1, clock : in std_logic;
              reset : in std_logic;
              q : out std_logic);
end dff_sync_res;

architecture dff_a of dff_sync_res is
begin
    process
    begin
       if (clock'event and clock ='1')
           if (reset = '1') then
               q <= '0';
           else
               q <= in1;
           end if;
       end if;
    end process;
end dff_a;

 

Flip-Flop with Synchronous Reset