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library ieee;
use ieee.std_logic_1164.all;

entity mux is
    port ( in1, in2 : in std_logic;
              sel : in std_logic;
              out1 : out std_logic);
end mux;

architecture mux_a of mux is
begin
    process (in1, in2, sel)
    begin
       if (sel = '1') then
           q <= in1;
       else
           q <= in2;
       end if;
    end process;
end mux_a;

 

2:1 Multiplexer

A multiplexer can also be described in the below two formats. One should should consider the relevant implementation based on the design circumstances.

architecture mux_a of mux is
begin
    process (in1, in2, sel)
    begin
       q <= in2;
       if (sel = '1') then
           q <= in1;
       end if;
    end process;
end mux_a;
architecture mux_a of mux is
begin
    q <= in1 when sel = '1' else
             in2;

end mux_a;