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library ieee;
use ieee.std_logic_1164.all;

entity latch is
    port ( in1, clock : in std_logic;
             out1 : out std_logic);
end latch;

architecture latch_a of latch is
begin
    process (clock)
    begin
        if (clock = '1') then
            out1 <= in1;
        end if;
    end process;
end latch_a;