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library ieee;
use ieee.std_logic_1164.all;

entity dff_async_res is
    port ( in1, clock : in std_logic;
              reset : in std_logic;
              q : out std_logic);
end dff_async_res;

architecture dff_a of dff_async_res is
begin
    process 
    begin
       if (reset = '1') then
            q <= '0';
       elsif (clock'event and clock = '1')
            q <= in1;
       end if;
    end process;
end dff_a;

 

Flip-Flop with Asynchronous Reset