HDLPlanet Newsletter Sept 2003
-------------------------------------------------------------------------------
"When you do the common things in life in an uncommon way, you will command the
attention of the world." - George Washington
Editor's note :
I am not sure whether the way this newsletter is being started is common or
uncommon, but it definitely deserves the attention of the world... the VLSI
world.
Motorola chooses Microsoft Smartphone OS (Operating System) for their mobile
handsets. The move is significant to Microsoft since this gives an opportunity
for them to get into the mobile phone market as a competitor to Symbian. I use
a Motorola handset, now I should start thinking of my mobile phone crashing,
my mobile phone being the victim of any virus attack and the three buttons
(Ctrl+Alt+Del).
I. Tools in News
-------------------------------------------------------------------------------
1. VHDL Library Management : An application note from Novas. This article
provides information on how to specify VHDL library mapping in the Debussy
environment. A couple of ways of including Verilog blocks in a VHDL design
are also discussed.
http://www.novas.com/.docs/pg/2003-08-vhdl_library_management.html
2. The Best of Debug Tips : In this article, Novas presents Verdi to Debug
Problems with Data Paths.
http://www.novas.com/.docs/pg/2002-12-Verdi_Data_Path_Debug.html
II. Knowledge capsule
-------------------------------------------------------------------------------
o For the blooming professionals
Can we get rid of timing simulations with STA?
STA is a good technique to detect timing violations without performing actual
simulations of test patterns. STA checks for most of the timing paths in the
design. Usually designs have multiple modes of operation and care should be
taken such that all these modes are checked in STA. There are some timing
checks which cannot be done by STA namely,
- Asynchronous paths
- Glitches
- Dummy timing models
Asynchronous paths cannot be checked because STA tool checks all the timing
with respect to the clock edges. And similarly glitches.
For some modules in the design ( which are usually analogish in nature ), the
accurate timing information is not available. The examples of such modules
are ADC, PLL, etc. So the timing paths to/from these modules cannot be tested
with STA.
So the answer to the above question is NO. We still need timing simulations
to catch the above mentioned timing problems. Further more, its not always
possible in STA to check the various modes and conditions which the design is
supposed to operate in. Hence it is very important to run timing simulations
for the corner conditions ( this is decided by the designers ). And more over
it is gives the designer an added comfort level, if he has functional test
vectors passing in timing simulations at the rated speed.
o For the budding professionals
Why do we need modeling?
Any system in real life is a very complex system. If are supposed to analyze
or design these systems using computers, it is a very difficult task. There
are two things that needs to considered here,
1. How do you represent the different components of the system?
2. What are all the components of the system to be represented?
Lets take an example to understand this,
How do you model a car?
First lets look at the components of a car,
- 4 wheels
- 1 steering wheel
- brakes
- engine
- seats
- chassis
- ....
Lets assume that we are doing analysis with the brake system. Now we need to
look at, what all is relevant to the brake system?
- 4 wheels
- brakes
- engine
We are trying to study the dynamic mechanics of the brake system, all the above
required components can be represented in terms of vectors.
This answers the first question.
Depending upon what part of the system we are analyzing, we can represent the
relevant the vectors. For eg., if we are trying to study what happens when the
car is moving and when the engine is switched off, in this case we can omit the
engine vector representation.
By trying to reduce the number of vectors, all we are trying to do is reduce
the number of parameters required for analysis ( hence the compute time ), with
not much loss of accuracy.
I hope the above example makes the modeling requirements clear. I have
represented the example in a very crude way, this is fine, because the intent
being to give you an understanding of modeling and not to actually model the
car.
In the next part we will take a closer look at modeling.
III. Automation Arena
-------------------------------------------------------------------------------
This section is meant for tips in scripting for the design/verification
engineers. Lets begin with learning some Tcl.
Learning Tcl made easy - Part 1
Tcl Basics :
- It is string-based, interpreted command language
- It is similar to C in certain aspects
- Its simple syntax & semantics makes it easy to learn
Generic Syntax in Tcl :
command arg1 arg2 arg3...
Example : puts stdout "Hello World!!"
This command will print "Hello World!!" on the standard output.
Command Evaluation and Substitutions :
Whenever a command is specified the interpreter first evaluates all of its
arguments and only then executes the command. When evaluating the arguments,
it follows vertain rules viz.,
- $ variable substitution :
Wherever substitution is applicable, the string followed by the $ symbol,
is substituted by the variable represented by that string.
- \ backslash substitution :
This is the escape character for newline, $ and quotes.
Example : puts stdout "\$a"
This will print $a. $ substitution doesn't happen because of \
- Arguments surrounded by Double Quotes " "
spaces, tabs, newlines, semicolons inside are treated as ordinary
characters. Variable substitution, command substitution and backslash
substitutions take place as usual.
Example (i) : set a "BOY"
This command assigns the string "BOY" to the variable 'a'.
Example (ii) : set b "GOOD $a"
This command assigns the string "GOOD BOY" to the variable 'b'.
- Argument surrounded by Curly Braces { }
All special characters lose their meaning (no substitutions take place).
Braces defer evaluation. The { } braces can be nested
Example : set list {12 {78 5} 45 "Im a not a number"}
This will assign 12 {78 5} 45 "Im a not a number" to list
- Argument surrounded by [ ]
Everything inside [ ] is treated as a stand alone command or a tcl script
in case of multiple commands.
Example : set result [expr (4+6)/4]
This will assign 2 to the variable result
By now you have learnt two important commands (set, puts) also.
Now lets look at a simple tcl script :
set a "Hello"
set b "$a World!!
puts "$b \n"
set c [string range $b 0 3]
if {$c == "Hell"} {
puts "Oh god ! \n"
} else {
puts "Peace ! \n"
}
The output of this script will be :
Hello World!!
Oh god !
This might need some explanation about 4th statement. Here the statement
within [ ] is treated as a command and that will fetch first 4 characters of
the variable b. It is then assigned to the variable c.
Strings and Lists :
In tcl, the value of each variable is stored as a string. Even the numbers
are numbers are transformed into strings before assigning. "list" is a
special type of data representation here. It is nothing but a string with
spaces as the element separators. Lists can contain sub lists. Check the
following example for understanding.
Example :
set listi1 {12 {78 5} 45 "Im not a number"}
Here the list list1 contains the elements 12 {78 5} 45 "Im not a number"
set sublist1 [lindex $list1 1]
The list sublist1 gets the elements 78 5
set sublist2 [lindex $list1 3]
This list sublist2 gets the elements Im not a member
lindex $sublist2 1
This will be evaluated as not
Mathematical Expressions :
Though all variables are stored as strings. We can use the command 'expr' to
calculate mathematical expressions. This will internally use float & integer
representations.
Example :
set result [expr (4+6)/4]
The variable result will be assigned with the value evaluated in that
expression (2). In this case it uses integer representation internally.
set result [expr (4.0+6)/4]
In this cause it uses float representation internally and then assigns
2.5 to result.
How to display something :
We have already seen using the puts command to print/display messages or
variables that we intend to.
Example :
puts "This is just a message"
puts "This prints a variable $name"
There is a provision for formatted printing also:
set var 255
puts [format "The number %d is equal to 0x%02X" $var $var]
This will print :
The number 255 is equal to 0xFF
Other format specifies are %s for strings, %d for decimal, %f for real, %e
for real with mantissa-exponent form, %x for hexadecimal and %c for
characters.
Thats all in the first part of "Learning Tcl made easy".
-- End of Part 1 of Learning Tcl made easy --
IV. Editor fundas
-------------------------------------------------------------------------------
o Can you compare two files with VIM/GVIM ?
Yes, VIM supports comparing two files. How to use?
gvim -d <file1> <file2>
The above command, invokes gvim with the two files side by side, highlighting
the differences.
V. Humour
-------------------------------------------------------------------------------
What is an IC ??
IC is a large communal gathering of microscopic beings from dimension X who can
perform advanced calculations really really fast.
To elaborate, IC stands for Integrated Community. To the keen scientific
observer, it is a Small Plastic Thingy (SPT) with metal legs sticking out of it
that makes really cool avant garde jewellery.
Through its Many Microscopic Inhabitants (MMI), you can operate your computer,
your compact disc player, your television, and sometimes your car on this
Wonderful Little Device (WLD).
While the IC is useful for many different things, don't carry one in your back
pocket. The MMIs don't like to be sat on, and they'll send one Spear-bearing
Microscopic Inhabitant (SBMI) to each of the ICs legs to poke you in the butt.
-------------------------------------------------------------------------------
Disclaimer:
Unless otherwise stated the copyrights on all the information provided in this
newsletter and also the trademarks belongs to their respective owners. Keeping
the focus of HDLPlanet on knowledge sharing, the information here could be just
a collection from other sources. This newsletter also doesn't quote for any
particular company. The links provided here are verified at the time of
publishing of the newsletter. We don't guarantee the existence of the contents
in the links all time.
-------------------------------------------------------------------------------
HDLPlanet Newsletter Sept 2003