Much of today's logic design (synchronous) is based on two assumptions: all signals are binary, and time is discrete. Both of these assumptions are made in order to simplify logic design. By assuming binary values on signals, simple Boolean logic can be used to describe and manipulate logic constructs. By assuming time is discrete, hazards and feedback can be largely ignored. However, a system that can operate without these assumptions has the potential to generate better results.

Asynchronous circuits keep the assumption that signals are binary, but remove the assumption that time is discrete. This has several possible benefits: no clock skew, low power, average-case instead of worst-case performance, easing global timing issues, better technology migration potential, automatic adaptation to physical properties and robust mutual exclusion and external input handling. (All these have been discussed earlier).

With all the potential advantages of asynchronous circuits, one might wonder why synchronous circuits still predominate. The reason is that, asynchronous circuits have several problems as well. Primarily, asynchronous circuits are more difficult to design in an ad hoc fashion than synchronous circuits. In a synchronous system, a designer can simplify define the combinational logic required and surround it by latches. Setting clock rate to a long enough period, all worries about hazards & dynamic state of the circuit are eliminated. On the other hand designers of asynchronous circuits must pay great deal of attention to the dynamic state of the circuit. Hazards must be eliminated or shouldn't be introduced in the first place, to avoid incorrect results. Ordering of operations must be carefully ensured. For complex designs these issues get significantly multiplied. Unfortunately existing CAD tools can't really help in this aspect.

The above diagram portrays a synchronous communication system. It uses an external global clock for providing a time base that determines what events occurs when. On the first clock edge, the sender register samples the data on its input and projects at its outputs. Data passes through the combinatorial logic and on the second clock edge, receiver register samples this data and passes it to the output. Basically clock events serve as logical ordering of the system functions. And the delay corresponding to the combinatorial logic path along with the register delay is going to determine the system speed. In case of multiple pipeline stages, the slowest combinatorial logic path is going to dictate the system speed. Thus the delay involved in one stage is going to affect the system speed if it experiences the maximum delay. As said earlier "worst case delay" controls the throughput rate of the system.

Among several reasons due to to which a system can go into an unpredictable state is due to metastability in flip-flops, setup and hold time violations being the most common factors for metastability. For any flip-flop, it is an absolute necessity that the input data complies with both setup and hold time requirements. On  a  good  flip-flop, when you meet the setup  and hold  window,  it always gives you  a  solid  output within the guaranteed maximum Clk-Q delay. Hence yet another principle followed is that the input data must stay unchanged within a setup-hold window around the clock edge.

Asynchronous Communication

This diagram portrays an asynchronous communication system. There is no global clock involved in this case. Internally generated events/signals are going to take care of the ordering of the system functions. Once the sender register has sampled the input data, it sends a request to the next stage and waits for the acknowledgement. On receiving the acknowledgement, sender sends the data and it reaches the receiver register via the combinatorial logic.

This operation will become more clear as you go further. In this section I just wanted to show the difference between synchronous and asynchronous communication. Asynchronous communication follows the handshake principle. Two stages mutually request and acknowledge for their operations. Thus in case of multistage pipelines, the delay involved in one stage is not going to hurt other stages. Here it is the "average case delay" that enables substantially higher throughput rate as against synchronous systems.

Handshake can be implemented using either "Delay Padding" or "Completion Detection"

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Last Updated on 25th Feb 2002