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 Asynchronous Design
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 What is Asynchronous Circuits ?

Circuits that operate by local negotiations rather than under the control of a global clock  are termed as "asynchronous circuits" or "self-timed circuits". Asynchronous designs offer an interesting alternative by keeping the assumption that signals are binary but removing the assumption that time is discrete. Asynchronous design as an alternative to synchronous design is a theoretical realization that warrants some attention.

 
Brief Overview of Advantages of Asynchronous Designs.

Since the clock has served the industry so well for so long, one must have fair enough reasons to consider dispensing with its services and look forward towards clock-less designs (self-timed or asynchronous designs). Several arguments have been used to justify abandoning the known and trusted synchronous design methodology. Though some of the arguments don't seem to be wholly convincing, when taken together they make a reasonable case for further research.

Every synchronous designer is burdened with the fundamental assumption that "all signals are binary and time is discrete. Many are now realizing that their most difficult problems surround these basic assumptions. Problems which seriously impact their final results are clock skew, power consumption, critical path delays, metastability, etc. By eliminating these restrictions, a design can reach higher level of performance. Asynchronous design offers an interesting alternative by keeping the restriction that signals are binary but realizing that time is not discrete. Asynchronous design is a theoretical realization that warrants some attention. However, as of now we have to be content with the rather diffuse arguments. Asynchronous designs claim to yield better results in the following areas of designer's interest: Power efficiency, Modularity, Performance, Clock Skew, Concurrency and Metastability.

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Detailed Review of its Advantages over Synchronous Designs.

As said above, there are several arguments which aren't wholly convincing though they make a reasonable case for research together. Perhaps, this is the reason why much of the work is still carried out in academia. Industries require rather firmer ground to justify redirecting their development resources. Lets see if the following arguments can fetch something!!!

  • Power Efficiency : Reducing power consumption has become critical with the advent of battery operated consumer electronics. Design constraints for this class of product require strict power constraints. In synchronous circuits, clocks beat away, causing power dissipation whether or not the circuit is doing useful work. For example, even though the floating-point unit on a processor might not be used in the current instruction stream, the unit still is operated by clock. Clock gating and dividing alleviates this problem, but only on a coarse granularity, moreover that again needs additional hardware. Asynchronous circuits are inherently data driven and only uses power for useful work. Though asynchronous circuits seem to be needing more transitions on the computation path than synchronous circuits, they generally have transitions only in the areas involved in the current computation. The Philips digital audio error detector chip based on the asynchronous design methodology supports the power efficiency claim. It demonstrates a factor of five power reduction over its synchronous counterparts built on the same technology.
  • Modularity : Clock is a global signal. Handling multiple clock domains in synchronous designs is not an easy task. Interfacing two FSMs that were designed with different clock requirements or operating at different frequencies is very difficult. Asynchronous designs have clean interfaces and avoid this problem. The modularity problems with clocked circuits only arise if design components are ported below the RT level. If they are ported as behavioral descriptions, a synthesis tool should be able to generate a new RT structure to suit a new clock period. A perspective which is often applied is to look to a future where a billion transistors are available on a chip and to argue that the modularity case will then be compelling, but even here the problem can be removed by sufficiently powerful abstraction and synthesis tools.
  • Performance : In any synchronous design's pipelined datapath, the data marches through the operation chain (recall we have pipeline registers between any two pipeline stage) under the command of the clock. Clock period is chosen to be larger than the worst-case delay of each pipeline stage. The throughput of this is equivalent to the number of data samples processed per second which in turn is equivalent to the clock rate. In other words, throughput of a pipelined system is directly linked to the worst-case delay of the slowest element in the pipeline. On an average, the delay of each pipeline stage is smaller. The same pipeline could support an average throughput rate that is substantially higher than the synchronous one. Throughput here is proportional to the worst-case delay of the slowest stage multiplied by the number of pipeline stages. The performance of microprocessors and computer peripheral designs are heavily effected by internal timing. The term "critical-paths" evolved to describe signal paths in designs that limit the overall circuit performance. Every good designer knows that critical-paths if reduced will directly effect the design's performance (processing speeds). Asynchronous design's exhibit average-case performance as against worst-case performance. Clearly, the critical timing of a circuit is enhanced when comparing average case scenarios to worst case scenarios. Synchronous designs cannot avoid worst-case performance since all possible computations must be complete before results can be latched. On the other hand asynchronous designs are free from the dilemma since the circuitry is capable of sensing the computations completion.
  • Clock Skew : Synchronous designs assume that all clock events or timing references happen simultaneously over the complete circuit. This in fact is not the reality, because of the "clock skew" effects. Clock skew is fast becoming the single most difficult phenomena to protect a circuit against it. As clocks get faster, chips get better and tracks get thinner, it is increasingly hard to keep clock skew within tolerable limits. The engineering effort and silicon resource that goes into the clock distribution network on today's high-end processors illustrate the scale of the problem. Asynchronous designs have no clocks and hence do not suffer from clock-skew. The performance and clock skew arguments are related. High performance of the today's high end processors does not appear in general to be incompatible with power-efficiency, and adding clock gating to improve power-efficiency compromises clock skew thereby adversely affects performance, but a direct comparison between high performance clocked and asynchronous circuits is difficult because of the imbalance in the resources available to the two methodologies.
  • Concurrency : Most abstract representations of concurrent systems map far more naturally onto asynchronous circuits than they do onto clocked circuits. This however is depending on the tools support which is not yet widely available.
  • Metastability Any asynchronous input (any input from outside world) to a clocked circuit represents a source of unreliability, since there is always some residual probability that the synchronization circuit will fail. Metastability wreaks havoc in synchronous systems. It is caused by unstable equilibrium state for example when a pair of cross coupled CMOS inverters are stuck at mid-voltages it is impossible to determine how long such a state persists. Unfortunately, due to the complexities in today's systems, it is not possible for the designer to avoid this type of situation. Asynchronous systems naturally handle mutual exclusivity since they can wait an arbitrarily long time for such a condition to stabilize. Also since these systems are not bounded by global clock, inputs from external world are accepted more gracefully since they are naturally asynchronous.
  • Easing of Global Timing Issues : In systems such as a synchronous microprocessor, the system clock, and thus system performance, is dictated by the slowest (critical) path. Thus, most portions of a circuit have to be carefully optimized to achieve highest clock rate, including rarely used portions of the system. Since many asynchronous systems operate at the speed of the circuit path currently in operation, rarely used portions of the circuit can be left unoptimized without adversely affecting the system performance.
  • Better Technology Migration Potential : Integrated circuits will be implemented in several technologies during their lifetime. Greater performance for a synchronous system can be obtained by migrating all system components to a new faster technology, since the overall performance is again based on the longest path. In asynchronous systems, migration of only the more critical system components is possible and can improve system performance. Also since many asynchronous systems sense computation completion, components with different delays may often be substituted into a system without altering other elements or structures.
  • Automatic Adaptation to Physical Properties : Delay through a circuit can change with the variations in temperature, power-supply voltage, fabrication and other physical factors. Synchronous circuits must take into consideration of the worst possible combination of these factors and thus determine the clocking speed. But asynchronous circuits sense computation completion, and will run as quickly as the current physical properties allow.
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Obstacles to Asynchronous Design
  • Testability : Although one can argue that power consumption, performance, EMI, etc., of asynchronous signals are very real, so are the threats. The most frequently cited argument against asynchronous design is the difficulty of production testing asynchronous devices. Much less is known about the testability of such circuits, and design margin characterization poses a significant problem. Production test equipment is heavily committed to using a clock to regulate the application of stimuli and to time the sampling of responses from the device under test. Timing driven test equipment is particularly not suitable for testing event-driven asynchronous circuits. In addition, asynchronous circuits tend to require logically redundant gates to remove hazards, and these are un-testable by normal methods. Economic testability is an absolute requirement for volume production.  

  • Design Tools Support : Design tool support is another area of difficulty. Modern CAD tools are aimed at clocked circuits, and though it is clearly possible to design a clockless circuit using them, they could be lot more helpful, if the tools were targetted for clockless designs. For example, most synthesis tools will automatically remove logically redundant gates that were carefully inserted to remove hazards. Recent developments however, prove the feasibility of CAD tools targetted for asynchronous designs, and it is just a matter of time before large asynchronous designs enter the commercial arena.

  • Design Practice : Perhaps, the biggest obstacle to the acceptance of asynchronous design techniques assuming their merits can be demonstrated irrefutably, is the aversion of the design community. Engineers have been trained to avoid asynchronous operation, though it was used in the distant past. This causes that the designers will be reluctant to suggestions to revert back to asynchronous design methodologies that were rejected a few of decades ago.

 

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Last Updated on 25th Feb 2002

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